The present invention relates to an arithmetic processing device for obtaining output data during each sampling period, using the input data during the sampling period and the output data during a few preceding sampling periods of a digital filter or the like.
In general, an output Y(t) of a second-order recursive digital filter is given by: EQU Y(T)=X(T)-B1.Y(T-1)-B2.Y(T-2) (1)
where X(T) is input data, B1 and B2 are coefficients, and T is the current sampling period number (=0, 1, . . . ).
FIG. 1 shows a block diagram of a conventional second-order recursive digital filter. Variables X(T), Y(T), Y(T-1) and Y(T-2) are stored in a register file 10, while coefficients +1, -B1 and -B2 are stored in a coefficient register 12 (e.g., a ROM). The address signals for accessing the register file 10 and the coefficient register 12 are provided by a control store 14. The control store 14 thus produces address signals in a predetermined order for each sampling period. Sample input data X(T) and sample output data Y(T) to be described later are supplied to the register file 10. Outputs from the register file 10 and the coefficient register 12 are supplied to a multiplier 16, and the multiplied product outputs therefrom are supplied to an accumulator 18 through an adder 17. The accumulator 18 is cleared by the control store 14. The output Y(T) from the accumulator 18 is provided as the output from the digital filter.
The digital filter of the configuration as described above operates in the manner to be described below for each sampling period. The input data X(T) is stored in address "00" of the register file 10. Before this time point, the immediately preceding output data Y(T-1) and the output data Y(T-2) which immediately precedes the data Y(T-1) have been respectively stored at addresses "10" and "11" of the register file 10. When the input data X(T) is stored, the current output data Y(T) may now be calculated. Note that the accumulator 18 is in the cleared state at this point. The control store 14 calculates according to the above-stated relation (1) based on the outputs from the register file 10 and the coefficient register 12 using the multiplier 16, an adder 17 and the accumulator 18. The output Y(T) from the accumulator 18 is stored in address "01" of the register file 10. Output data Y(T), Y(T-1) and Y(T-2) respectively become Y(T-1), Y(T- 2) and Y(T-3) in the next sampling period. However, the control store 14 produces the same address signals for the same data. More specifically, the control store 14 always produces an address signal "10" for accessing the immediately preceding output data Y(T-1). For this reason, in the next sampling period, Y(T-2) is used where Y(T-1) would be used. In view of this, when the arithmetic operation is completed and the current output data Y(T) is stored in the register file 10, data are transferred within the register file 10. More specifically, the data Y(T) and Y(T-1) stored in addresses "01" and "10" of the register file 10 are respectively shifted to addresses "10" and "11". Then, in the next sampling period, the current and immediately preceding output data Y(T), Y(T-1) are respectively handled as the immediately preceding output data Y(T-1) and the output data Y(T-2) which immediately precedes the output data Y(T-1), thus solving the above problem.
In this manner, the conventional digital filter requires transfer of output data within the register file after each sampling period. This degrades the data processing speed. This problem becomes more pronounced as the order of the filter becomes higher. In general, a single arithmetic circuit comprises more than one digital filter. In order to fit more than one filter into a single arithmetic circuit, the processing time per digital filter must be reduced to the minimum.